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A 0.08p2-sized 8F2 Stack DRAM cell for multi-Gigabit DRAM
Hyunpil Noh, Suock Jeong, Seongjoon Lee, Yousung Kim, Woncheol Cho, Min Huh, Gucheol Jeong,
Jaebuhm Suh, Hoyeop Kweon, Jaesung Roh, Kisoo Shin, and Sangdon Lee
Device BT Team, Memory R&D Division, Hynix Semiconductor Co. LTD, San 136-1, Ami-Ri,
Bubal-Eun Ichon-Si. Kvungki-Do. 467-70 1 Korea

Abstract
The first 8F2 Stack DRAM cell with 0.08pm’ size has
been successfully integrated employing poly plug scheme
for landing plug contacts and W/poly gates and Ru MIM
capacitors, of which cell working has been proven under
easy function check mode. Cell transistor with W gate
technology exhibits a sufficient saturation current(bP) of
-40~1A with threshold voltage (Vbat) of 0.9V and
satisfactory ring oscillator delay characteristics of - 5Ops.

INTRODUCTION
The first principle in DRAM integration would be
miniaturization of cell in the viewpoint of cost reduction. In
this study, we have integrated 0.08pm2-sized 8F2......

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Approximate Word Count: 880
Approximate Pages: 4 (250 words per double-spaced page)

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