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Engineering Plan
SC312 Final Project
11/7/04

*Names*

We plan to implement the basic multi-cycle processor design as shown in the textbook, as well as pipelining and "jump and link". The toughest part of this design will be the datapath control, for which we will be using a FSM. The ALU will implement add, sub, and, or, sll, and slt functions – though a separate block is typically used for shift operations, we felt that putting sll and srl in the ALU would simplify our design. All other basic functions (lw, sw, lui, beq, bne, j) will be implemented as show in the textbook.

The processor will have two main stages: load instructions into memory and execute instructions. Special instruction codes will be defined as "stall" and "stop execution" to work in conjunction with the FSM. The global reset will set all memory and registers to 0, and put the FSM in "load instructions mode". We would like to use one memory module to store both instructions and data (with instructions......

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Approximate Word Count: 384
Approximate Pages: 2 (250 words per double-spaced page)

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